Ferroelectric memories which use a ferroelectric film as a capacitor insulating film recently have received attention as a highly-integrated nonvolatile memory that utilizes polarization reversal and remanent polarization of the ferroelectric film.
As such a ferroelectric memory, a capacitor over bit line (COB) cell structure in which a capacitor insulating film is arranged above a bit line is proposed in Japanese Patent Application Publication No. 2004-119937 and H. J. Joo, et. al., 2004 Symposium on VLSI Technology Digest of Technical Papers, pages 148-149, for example.
According to the layout proposed by H. J. Joo, et. al., for example, in rectangular-shaped memory cells arranged to form a matrix, two word lines are arranged in a long side direction per unit memory cell (see FIG. 3). One of the word lines is a select word line, and the other of the word lines is a passing word line. One bit line is arranged in a short side direction per unit memory cell. Each wiring is ideally formed with the minimum processing dimension. Accordingly, when the minimum processing dimension is referred to as a feature size (hereinafter, simply denoted by “F”), the size of a unit cell is 4 F on the long side and 2 F on the short side, and the area of the unit cell is 2 F×4 F=8 F2.
The capacitor size in the layout by H. J. Joo, et. al. is 3 F on the long side and 1 F on the short side, and the area of the capacitor is 3 F2.
Here, there is a problem that the capacitor layout by H. J. Joo, et. al. has a large ratio of 3:1 between the long side and the short side. It is generally known that characteristic degradation occurs in a ferroelectric film during the manufacturing process due to plasma damage, hydrogen reduction, or the like. The characteristic degradation occurs in an edge region of the ferroelectric film. Accordingly, the longer perimeter length of the capacitor may cause the more characteristic degradation of the ferroelectric film.
One of specific examples of the characteristic degradation is that a signal amount from a memory cell decreases and thus reliability as a memory element decreases.
Assume that a region extending by (¼)F from each edge is a region not contributing to a signal due to characteristic degradation in the manufacturing process. In the capacitor with an area of 3 F2, a region having signals is reduced to 1.25 F2. In other words, the signal amount from the capacitor is reduced to 42% due to the influence of the characteristic degradation in the manufacturing process.
The size of the region to be damaged is constant independent of the size of the capacitor. Accordingly, the decrease in signal amount under the influence of the characteristic degradation becomes larger as the minimum processing dimension is reduced.